Demands on semiconductor devices with regard to scale integration, access speed and energy consumption are steadily increasing. In order to meet these demands, circuit devices may be scaled down. Scaling down of circuit devices such as field effect transistors (FETs) may, however, be accompanied by undesired physical effects, e.g., the so-called short channel defect, becoming noticeable in FETs having small channel lengths.
A method allowing manufacture of an integrated circuit with small minimum feature sizes would thus be desirable.